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INTEGRATED CIRCUITS
74LVC02A Quad 2-input NOR gate
Product specification Supersedes data of 1997 Aug 11 IC24 Data Handbook 1998 Apr 28
Philips Semiconductors
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
FEATURES
* Wide supply range of 1.2V to 3.6V * Complies with JEDEC standard no. 8-1A * Inputs accept voltages up to 5.5V * CMOS low power consumption * Direct interface with TTL levels * 5-volt tolerant inputs, for interfacing with 5-volt logic
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf v2.5 ns SYMBOL tPHL tPLH CI CPD PARAMETER Propagation delay nA, nB to nY Input capacitance Power dissipation capacitance per gate
DESCRIPTION
The 74LVC02A is a high performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC02A provides the 2-input NOR function.
CONDITIONS CL = 50 pF; VCC = 3.3 V Notes 1 and 2
TYPICAL 2.8 5.0 28
UNIT ns pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC02A D 74LVC02A DB 74LVC02A PW NORTH AMERICA 74LVC02A D 74LVC02A DB 74LVC02APW DH DWG NUMBER SOT108-1 SOT337-1 SOT402-1
PIN CONFIGURATION
1Y 1A 1B 2Y 2A 2B GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4Y 4B 4A 3Y 3B 3A
PIN DESCRIPTION
PIN NUMBER 1, 4, 10, 13 2, 5, 8, 11 3, 6, 9, 12 7 14 SYMBOL 1Y - 4Y 1A - 4A 1B - 4B GND VCC Data inputs Ground (0 V) Positive supply voltage NAME AND FUNCTION Data outputs
SV00389
1998 Apr 28
2
853-2019 19310
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
LOGIC SYMBOL
LOGIC DIAGRAM (ONE GATE)
A Y 2Y 3Y 4Y 4 10 13 B
2 3 5 6 8 9 11 12
1A 1B 2A 2B 3A 3B 4A 4B
1Y
1
SV00820
FUNCTION TABLE
INPUTS OUTPUTS nB L H L H nY H L L L nA
SV00390
LOGIC SYMBOL (IEEE/IEC)
2 3 5 6 8 9 11 12 1 1
L L H H NOTES: H = HIGH voltage level L = LOW voltage level
1
4
1
10
1
13
SV00391
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC Input voltage range DC output voltage range Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC +85 20 10 V V V V C ns/V UNIT
1998 Apr 28
3
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
ABSOLUTE MAXIMUM RATINGS1
Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage (for max. speed performance) DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +5.5 "50 -0.5 to VCC + 0.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II ICC ICC Input leakage current Quiescent supply current Additional quiescent supply current per input pin VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0 1 "0.1 0.1 5 VCC*0.5 VCC*0.2 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 10 500 A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
1998 Apr 28
4
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN tPHL/tPLH Propagation delay nA, nB to nY Figures 1, 2 1.5 TYP1 2.8 MAX 4.6 MIN 1.5 VCC = 2.7V TYP1 3.2 MAX 5.6 VCC = 1.2V TYP 11 ns UNIT
NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25C.
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V VM = 0.5 S VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load.
VI nA, nB, INPUT VM
TEST CIRCUIT
VCC S1 2 < VCC Open GND
PULSE GENERATOR
VI D.U.T. RT
VO
500
CL
50pF
500
GND tPHL VOH nY OUTPUT VM tPLH VCC t 2.7V 2.7V - 3.6V VI VCC 2.7V Test tPLH/tPHL S1 Open
SY00077 SV00392
VOL
Waveform 2.
Load circuitry for switching times.
Waveform 1. Input (nA, nB) to output (nY) propagation delays.
1998 Apr 28
5
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1998 Apr 28
6
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
1998 Apr 28
7
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
1998 Apr 28
8
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
NOTES
1998 Apr 28
9
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LVC02A
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04477
Philips Semiconductors
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